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Hamarsoft"s 86BUGS list

Undocumented/buggy instructions of x86 processors

(by harald feldmann)

The 86BUGS list, distributed with Ralf Brown's Interrupt list, is maintained and provided to you by Hamarsoft, the maker of the HAP & PAH datacompression program. Latest version of HAP & PAH is 3.14e.


This article is online from 2934 days and has been seen 5257 times


This is 86BUGS list revision level 04, issued November 3rd 1994.
(C) Copyright 1993, 1994 By Harald Feldmann.

This file lists undocumented and buggy instructions of the Intel 80x86
family of processors as well as features of processors compatible with
Intel products. Note that Intel does not support the special features and
may decide to drop opcode variants and instructions in future products.
Wherever the notation 88,86,87,186,286,287,287xl,386,386sx,387,387sx,
486,486sx,487 and Pentium is used, Intel CPUs are referenced unless
noted otherwise.

(*** For full document please download it ***)

...snip...
-------------------------------------------------------------------------
CPUID Identify CPU on 486 and higher CPUs
-------------------------------------------------------------------------
Mnemonic: CPUID
Opcode : 0F A2
Bug in : Is undocumented for 486, seems not to work on tested AMD 486s
Officially introduced as a new instruction with the Pentium.

Function:
Identifies CPU and revision information for the installed CPU. Note that
Intel officially introduced CPUID only with the Pentium processor.
It seems the instruction was unofficially introduced in the later
486 CPUs as well. Discovered by Christian Ludloff (see acknowledgements).
Supported by the UMC U5S 486 clones as well.

Executing it on an early 486 yields an Invalid Opcode Exception.
To safely use this instruction, an exception handler must be installed.
A safer workaround though is to test whether the ID bit in EFLAGS is set.
If so, the CPU supports CPUID. See <EFLAGS> image.

The instruction expects input in the EAX register and outputs information
in the EAX, EBX, ECX and EDX registers.

Input: EAX = 0000 0000 : Check CPU 486+ installed

Output: after CPUID:
EAX = 0000 0001 : OK, instruction supported
EBX = 756e 6547 : 'uneG'
EDX = 4965 6e69 : 'Ieni'
ECX = 6c65 746e : 'letn'
effectively the CPU says 'GenuineIntel'

Officially this returns a 'vendor string', which may indicate other than
Intel strings for OEMs.
The UMC U5S-33 returns 'UMC UMC UMC ' or ' UMC UMC UMC' (untested).

Input: EAX = 0000 0001 : Obtain model specific information

Output: after CPUID:
EAX = RRRR RFMS : revision information
R = Reserved Zero, but reserved
F = Family (4=486, 5=Pentium)
M = Model (3 on tested 486DX-2/66, 1 on tested Pentium/60)
S = Stepping (5 on tested 486DX-2/66, 3 on tested Pentium/60)
EBX = RRRR RRRR
R = Reserved Zero, but reserved
ECX = RRRR RRRR
R = Reserved Zero, but reserved
EDX = xxxx xxxx : Bitmapped features, 1 means option available
Bit 0 = FPU built-in (supported on 486 and Pentium)
Bit 1 = V-86 mode extensions present
Bit 2 = I/O breakpoints possible
Bit 3 = 4 MB paging supported
Bit 4 = Time Stamp Counter present
Bit 5 = Has Pentium compatible Model Specific Registers
Bit 6 = Reserved (0)
Bit 7 = Machine Check Exception supported (P5 only)
Bit 8 = CMPXCHG8B supported (apparently Pentium only)
Bits 9-31 Reserved
Assume zero if bit is not mentioned.

Note that this instruction is not supported on all 486 CPUs. However,
Christian Ludloff has tested it on some 486 DX and 486 SX models, in
addition to the Pentium/60 and found them to be present on those machines.
Any step and model information you find this instruction to run on is
welcomed. Please forward it to Christian.

Apparently all new(er) Intel CPUs are equipped with (some) of these
extensions, not just the Pentium.
...snip...

(*** For full document please download it ***)


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