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Timing on the PC family (rel.3)

Over 290 pages on programming 8253/8254

(by kris heidenstrom)

Timing on the PC

This archive contains a technical document useful to PC programmers, with many sample programs. The document covers timing and related subjects on the IBM PC family under DOS. Subjects include BIOS and DOS functions, the BIOS tick count, hardware interrupts, timer tick interrupts, Port B, the 8253/8254 timer, speeding up the timer tick, dynamic tick periods, simulated vertical retrace interrupt, double and triple buffering, absolute timestamping, the RTC, other timing methods, reading the joystick, PWM sound generation.
Freeware. 13400 lines.

This article is online from 3006 days and has been seen 6723 times


pctim003.zip
Timing on the PC family (rel.3)
Kris Heidenstrom
20-12-1995


Timing on the PC

This archive contains a technical document useful to PC programmers, with many sample programs. The document covers timing and related subjects on the IBM PC family under DOS. Subjects include BIOS and DOS functions, the BIOS tick count, hardware interrupts, timer tick interrupts, Port B, the 8253/8254 timer, speeding up the timer tick, dynamic tick periods, simulated vertical retrace interrupt, double and triple buffering, absolute timestamping, the RTC, other timing methods, reading the joystick, PWM sound generation.
Freeware. 13400 lines.

1 INTRODUCTION AND DOCUMENT INFORMATION
1.1 Document Overview
1.1.1 Audience
1.2 Contents
1.3 Author and Distribution
1.4 Disclaimer and Legal stuff
1.5 Document Conventions
1.6 Sample Code Conventions
1.7 Acknowledgements
1.8 Quoter Program
1.9 Revision notes
1.10 Glossary
2 OVERVIEW OF TIMING TECHNIQUES
2.1 The Big Picture
2.2 Which Technique?
2.3 Comparison of Techniques
2.4 Other Subjects Covered in this Document
3 DOS AND BIOS TIME-OF-DAY AND ALARM FUNCTIONS
3.1 Reading the Date and Time from DOS
3.2 Reading the Date and Time from the BIOS
3.3 Sample Program: DOS Device Driver for the AT Clock
3.4 Other BIOS Time and Alarm Functions
3.5 Other Other BIOS Time Functions
3.6 The Times They Are A-Changin'
4 USING THE BIOS TICK COUNT VARIABLE
4.1 The BIOS Tick Count Variable
4.2 Change of Day
4.3 Reading and Setting the Tick Count
4.4 Special Requirements - None
4.5 Sample Program: Reading the Tick Count
4.6 Sample Code: Optimised Function to Read the Tick Count
4.7 Sample Program: Using the Tick Count for Timeout Checking
4.8 Simple Delays using the BIOS Tick Count
5 SPECIAL SOFTWARE PRECAUTIONS
5.1 The Ctrl-C and Ctrl-Break Interrupts
5.2 Handling the Ctrl-C Interrupt
5.3 The Critical Error Interrupt
5.4 Critical Error Handler Parameters
5.5 Critical Error Handler Operation
5.6 The Divide Overflow Interrupt
5.7 Error Handling System
5.8 Sample Code Module: Critical Error Handler module
6 INTERRUPTS
6.1 The Timer Tick Interrupts
6.2 Interrupt Vector Table
6.3 Intercepting an Interrupt
6.4 Interrupt Hardware
6.5 IRQ to Interrupt Mapping
6.6 Interrupt Flag, Interrupt Acceptance, Interrupt Nesting
6.7 EMM386 Interrupt Interception
6.8 Avoiding EMM386 Overhead
6.9 Long Timer Tick Interrupt Handlers
6.9.1 Danger of Long Timer Tick Interrupt Handlers
6.10 Interrupt Mask Register
6.11 Enabling and Disabling the Timer Tick Interrupt
6.12 Reading the Interrupt Request Register
6.13 Reading the Interrupt In Service Register
6.14 When You Should Disable Interrupts
6.15 When You Shouldn't Disable Interrupts
6.16 Causes of Interrupt Delivery Jitter and Fast Tick Loss
6.16.1 Interrupt Delivery Jitter due to Real Interrupts
6.16.2 Interrupt Delivery Jitter due to Software Interrupts
6.16.3 Interrupt Delivery Jitter due to Hardware Accesses
6.16.4 Avoiding Interrupt Delivery Jitter
6.17 Detecting Interrupt Delivery Jitter and Missed Fast Tick Interrupts
6.18 Disabling Interrupts for Longer than One Timer Tick
6.19 Disabling Interrupts for Long Periods of Time
6.20 Overhead of an Interrupt
6.21 Effect of Background Interrupts
6.22 Safe Control of Interrupts
6.23 Timer Tick Interrupt Handler Guidelines
6.24 Accessing Hardware Devices in an Interrupt Handler
6.25 Calling DOS and BIOS in an Interrupt Handler
6.26 Calling C Library Functions in an Interrupt Handler
6.27 Re-entry of Interrupt Handlers
6.28 The 'End Of Interrupt' Signal
6.28.1 Level-Triggered Interrupt Reset
6.29 Enabling and Disabling Interrupts in an Interrupt Handler
6.30 Stack Usage and Stack Checking in an Interrupt Handler
6.31 Chaining to the Old Interrupt Handler
6.32 Writing Interrupt Handlers in Assembly Language
6.32.1 Assembly Language Interrupt Handlers: Accessing Variables
6.32.2 Assembly Language Interrupt Handlers: Starting Condition
6.32.3 Assembly Language Interrupt Handlers: Preserve the Registers
6.33 Using Interrupt Eight in a TSR
6.34 Using int 8 Without Chaining
6.35 Using int 1C hex instead of int 8
6.36 Sample Program: Using int 1Ch With Critical Error and Ctrl-C Handling
6.37 Debugging Interrupt Handlers
7 HARDWARE INFORMATION AND PROGRAMMING
7.1 The 14.31818 MHz Clock
7.2 Clock Frequency Accuracy
7.3 The Counter/Timer Chip (CTC)
7.4 CTC Channels
7.4.1 CTC Channel Zero
7.4.2 CTC Channel Zero Default Operating Mode
7.4.3 CTC Channel One
7.4.4 CTC Channel Two
7.5 Speaker Interface
7.6 CTC Internal Registers
7.7 Access Modes
7.8 CTC Operating Modes
7.8.1 Operating Modes: Behaviour Common to All Modes
7.8.2 Operating Mode Zero: Interrupt on Terminal Count
7.8.3 Operating Mode One: Hardware-Retriggerable One-Shot
7.8.4 Operating Mode Two: Rate Generator
7.8.5 Operating Mode Three: Square Wave Generator
7.8.6 Operating Mode Four: Software-Triggered Strobe
7.8.7 Operating Mode Five: Hardware-Triggered Strobe
7.9 The 8254/8253 Registers
7.9.1 The Mode/Command Register
7.9.2 The Data Ports
7.9.3 Accessing the Registers
7.9.4 I/O Recovery Delays
7.10 Programming the Mode and Reload Register
7.11 Effect of Reprogramming Channel Zero on the Timer Tick Interrupt
7.12 Sample Program: Programming the Mode and Reload Value
7.13 Reading the Reload Register
7.14 Reading the Counting Register
7.15 The Latch Command
7.15.1 Meaning of Count Value in Mode Two
7.15.2 Meaning of Count Value in Mode Three
7.16 Sample Code: Reading the Count in Mode Two
7.17 The Lobyte/Hibyte Flag
7.18 The Read-back Command
7.19 Sample Code: Read-back
7.20 Reading the Count in Mode Three (8254 only)
7.21 Sample Code: Reading the Count in Mode Three
7.22 Sample Code: Optimised Mode Three Count Reading Function
7.23 Sample Program: Manipulate the CTC and Port B
7.24 Hardware Problems and Differences
7.24.1 Differences Between the Intel 8253 and 8254
7.24.2 Chipset Implementations
7.24.3 Intel 8253/8254/82C54 Clock Synchronisation Problems
7.25 Is the CTC an 8253 or an 8254?
7.26 Determining the Exact State of the CTC
7.27 Sample Program: Report Channel States
7.28 CTC Access under OS/2
7.28.1 OS/2 VTIMER.SYS: CTC Channel Zero
7.28.2 OS/2 VTIMER.SYS: CTC Channel One
7.28.3 OS/2 VTIMER.SYS: CTC Channel Two
7.29 Generating Audio Tones on the Speaker
7.30 Sample Program: Generating a Tone using CTC Channel Two
7.31 Timing Short Periods using CTC Channel Two
7.32 Timing Short Periods using Mode Three
7.33 Vertical Retrace
7.34 Sample Program: Timing Short Periods using Mode Three
7.35 The Real Time Clock (RTC)
7.35.1 Reading and Writing RTC Registers
7.35.2 Allocation of the RTC Registers
7.35.3 RTC Register A
7.35.4 RTC Register B
7.35.5 RTC Register C
7.35.6 RTC Register D
7.35.7 Reading the RTC
7.35.8 Sample Program: A TSR Clock using int 8 and the RTC
7.36 The RTC Interrupt and Related BIOS Functions
7.36.1 The BIOS Event Wait and Delay Functions
7.36.2 The BIOS RTC Interrupt Handler
7.36.3 Using the RTC Interrupt
7.36.4 Sample Program: Using the RTC Interrupt
7.37 Using CTC Channel One and Refresh Detect
7.37.1 Sample Program: Timing the Refresh Detect signal
7.37.2 Sample Code: delay(milliseconds) Function using Refresh Detect
8 SPEEDING UP THE TIMER TICK
8.1 The Fast Tick int 8 Handler
8.2 The Interface with the Mainline
8.3 Writing a Fast Tick Handler
8.4 Comments on Fast Timer Tick Interrupts
8.5 Sample Program: Morse Player using Fast Timer Tick
8.6 Dynamic Fast Tick Periods
8.7 Sample Program: Dynamic Fast Tick Interrupt Handler
9 READING AN ABSOLUTE TIMESTAMP
9.1 Sample Program: Absolute Time Reference (Timestamp) in Mode Two
9.2 Sample Program: Absolute Timestamp in Mode Two - Assembler
9.3 Handling the Midnight Boundary
10 OTHER TOPICS
10.1 The 586 Time Stamp Counter
10.2 Serial Port Regular Interrupt
10.2.1 Serial Port (UART) Documentation
10.2.2 Sample Program: Regular Interrupt using the Serial Port
10.2.3 Inserting Delays into Serial Port Transmitted Data
10.3 External Interrupt Sources
10.3.1 External Interrupt through Parallel Port
10.3.2 External Interrupt through Serial Port
10.3.3 External Interrupt through Sound Card
10.3.4 External Interrupt through Custom I/O Card
10.4 The Joystick Port
10.4.1 Joystick Port Hardware
10.4.2 Reading the Joystick Buttons and Position
10.4.3 Notes from the PC-GPE Article
10.4.4 Sample Program: Reading the Joystick Position
10.4.5 Using the Joystick Port for General Purpose Input
10.4.6 Joystick Left/Right and Up/Down Detection
10.5 The Mouse and Mouse Driver [not written]
10.6 Networks
10.7 Sound Generation
10.7.1 Pulse Width Modulation (PWM) Principle
10.7.2 PWM Audio Generation Implementation
10.7.3 Sample Program: DTMF Generation using PWM
10.7.3.1 Sample Program Explanation
10.7.3.2 Other Methods of Sound Generation
10.7.4 Peter Moylan's MUSIC Package
10.8 Related Software Packages
10.8.1 The ATIM Package
10.8.2 The MSCHRT and TCHRT Packages
10.8.3 The TCTIMER Package
10.8.4 The MILLISEC Package
10.8.5 The MSEC_12 Package
10.8.6 The ERTIMER Package
10.8.7 The FASTCLOK Package
10.9 Benchmarking Considerations
10.10 Granularity and Uncertainty
10.11 Converting between Microseconds and CTC Clocks
10.12 Maintaining a Millisecond or Microsecond Count
10.12.1 Sample Program: Millisecond Count using int 1Ch
10.13 Notes on Microsoft Windows
10.14 DOS File Date and Time Stamps
10.15 DOS and the Date and Time
10.15.1 DOS Date Rollover Bugs
10.16 Simulating a Vertical Retrace Interrupt
10.16.1 Vertical Retrace Interrupt Simulation Description
10.16.1.1 Measuring the Field Time
10.16.1.2 Controlling the CTC Interrupt
10.16.1.3 Significance of the SafeMargin Value
10.16.1.4 Overhead due to Large SafeMargin and Screen Update
10.16.1.5 Enhanced Handling of Missed Retrace Start
10.16.1.6 Other Notes
10.16.2 Sample Program: Simulating a Vertical Retrace Interrupt
10.16.3 Triple Buffering
11 QUESTIONS AND ANSWERS
11.1 Timing Accuracy
11.2 Timer Interrupts (int 8, int 1Ch, RTC Interrupt)
11.3 Interrupt Priorities and Nesting
11.4 Interrupt Handler Restrictions
11.5 High Speed Timer Tick
11.6 DOS Date and Time
11.7 Accessing Hardware
11.8 Miscellaneous
12 REFERENCES


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