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Motorola Instruction set table

MC68030 processor instruction description

(by bjorn ove arthun)

A reference that explains Motorola x030 instructions, showing synopsis, registers, syntax and output results.


This article is online from 2878 days and has been seen 5803 times




          Documentation on the MC68030 processor by Bjorn Ove Arthun
          Also known as Zynx/Inferiors (ex Imagina). or as Hei on irc


          I wrote this doc as there are no good docs on the 030. This doc
          will be ugraded a couple of times -  at least every month.
          The next version will include about 10 more pages about
          optimizing

          any ideas or suggestions contact:

          Bjorn Ove Arthun, ulsbergtunet 11, 4033 Forus, Norway
      

          I am a game developer. Check out my stargate 2000 game for the 
          Falcon on this web page:


          http://www-users.informatik.rwth-aachen.de/~neil/ad/


----------------------------------------------------------------------------

+--------------------------------------------------------------------------+
|Mnemonic   |Description              |Mnemonic |Description               |
+--------------------------------------------------------------------------+
|ACBD       |Add Decimal with Extend  |MULS     |Signed Multiply
|ADD        |Add                      |MULU     |Unsigned Multiply
|ADDA       |Add Address              |---------|---------------------------
|ADDI       |Add Immediate            |NBCD     |Negate Decimal with Extend
|ADDQ       |Add Quick               |NEG      |Negate
|ADDX       |Add with Extend          |NEGX     |Negate with Extend
|AND        |Logical AND              |NOP      |No Operation
|ANDI       |Logical AND Immediate    |NOT      |Logical Complement
|ASL, ASR   |Arithmetic Shift L/R     |---------|---------------------------
|-----------|                         |OR       |Logical inclusive Or
|Bcc        |Branch Conditionally     |ORI      |Logical inclusive Immediate
|BCHG       |Test Bit and change      |---------|---------------------------
|BFCLR      |Test Bit Field and Clr   |PACK     |Pack BCD
|BFEXTS     |Signed Bit Field Extract |PEA      |Push Effective Address
|BFEXTU     |Unsigned -----||-----    |---------|---------------------------
|BFFFO      |Bit Field Find First One |RESET    |Reset External Devices
|BFINS      |Bit Field Insert         |ROL, ROR |Rotate Left and Right
|BFSET      |Test Bit Field and Set   |ROXL,ROXR|Rotate with Extend
|BFTST      |Test Bit Field           |RTD      |Return and Deallocate
|BKPT       |Breakpoint               |RTE      |Return from Exception
|BRA        |Branch                   |RTM      |Return from Module
|BSET       |Test Bit and Set         |RTR      |Return from Restore Codes
|BSR        |Branch to Subroutine     |RTS      |Return from Subroutine
|BTST       |Test Bit                 |---------|---------------------------
|-----------|                         |SBCD     |Subtr. Decimal with Extend
|CALLM      |Call Module              |Scc      |Set Conditionally
|CAS        |Compare and Swap Operands|STOP     |Stop
|CAS2       |As above in Dual Mode    |SUB      |Subtract
|CHK        |Check Reg: Against Bound |SUBA     |Subtract Address
|CHK2       |Check Against Upper and  |SUBI     |Subtract Immediate
|           |Lower Bounds             |SUBQ     |Subtract Quick
|CLR        |Clear                    |SUBX     |Subtract with Extend
|CMP        |Compare                  |SWAP     |Swap Register words
|CMPA       |Compare Address          |---------|---------------------------
|CMPI       |Compare Immediate        |TAS      |Test Operand and Set
|CMPM       |Compare Memory to Memory |TRAP     |Trap
|CMP2       |Compare Register Against |TRAPcc   |Trap Conditionally
|           |Upper and Lower Bounds   |TRAPV    |Trap on Overflow
|-----------|                         |TST      |Test Operand
|DBcc       |Test Condition, Decrement|---------|---------------------------
|           |and Branch               |UNLK     |Unlink
|DIVS, DIVSL|Signed Divide            |UNPK     |Unpack
|DIVU, DIVUL|Unsigned Divide          |-------------------------------------
|-----------|                         |      CoProcessor Instructions 
|EOR        |Exclusive Or             |-------------------------------------
|EORI       |Exclusive Or Immediate   |cpBcc    |Branch Conditionally
|EXG        |Exchange Registers       |cpDBcc   |Test Condition, 
|EXT, EXTB  |Signed Extend            |         |Decrement and Branch
|-----------|                         |cpGEN    |Coprocessor General Instr.
|ILLEGAL    |Take Illegal Instruction |cpRESTORE|Restore Internal State
|           |Trap                     |cpSAVE   |Save Internal State
|-----------|                         |cpScc    |Set Conditionally
|JMP        |Jump                     |cpTRAPcc |Trap Conditionally
|JSR        |Jump to Subroutine       |---------+---------------------------
|-----------|                         | Unofficial Instructions
|LEA        |Load Effective Address   |-------------------------------------
|LINK       |Link and Allocate        |         |
|LSL, LSR   |Logical Shift Left and   |         |Not complete. :)
|           |Right                    |         |
|-----------|                         |         |
|MOVE       |Move                     |         |
|MOVEA      |Move Address             |         |
|MOVE CCR   |Move Condition Code Reg. |         |
|MOVE SR    |Move Status Register     |         |
|MOVE USP   |Move User Stack Pointer  |         |
|MOVEC      |Move Control Register    |         |
|MOVEM      |Move Multiple            |         |
|MOVEP      |Move Peripheral          |         |
|MOVEQ      |Move Quick               |         |
|MOVES      |Move Alternate Address   |         |
|           |Space                    |         |
+
|     Dual Mode: 64 bit processing intructions eg. Muls.l d0,d1:d2 
| The Destination Operand is in 64 bit format 
+--------------------------------------------------------------------------+
|              Addressing Modes and Assembler Syntax
+--------------------------------------------------------------------------+
|Address Modes Syntax
+--------------------------------------------------------------------------+

01. Data register direct Dn
------------------------------------------------------------
02. Address register direct An
------------------------------------------------------------
03. Address register indirect (An)+
    with postincrement 
------------------------------------------------------------
04. Address register indirect -(An)
    with predecrement
------------------------------------------------------------
05. Address register indirect (d16,An)
    with displacement
------------------------------------------------------------
06. Address register indirect (d8,An,Xn)
    with index (8bit displacement)
------------------------------------------------------------
07. Address register indirect (bd,An,Xn)
    with index (base displacement)
------------------------------------------------------------
08. Memory indirect postindexed ([bd,An],Xn,od)
------------------------------------------------------------
09. Memory indirect preindexed ([bd,An,Xn],od)
------------------------------------------------------------
0a. Absolute short        (xxx).W
------------------------------------------------------------
0b. Absolute long        (www).L
------------------------------------------------------------
0c. Program counter indirect (d16,PC)
    with displacement
------------------------------------------------------------
0d. Program counter indirect with (d8,PC,Xn)
    index (8-bit displacement)
------------------------------------------------------------
0e. Program counter indirect with (bd,An,Xn)
    index (base displacement)
------------------------------------------------------------
0f. PC memory indirect postindexed ([bd,PC],Xn,od)
------------------------------------------------------------
10. PC memory indirect preindexed ([bd,PC,Xn],od)
------------------------------------------------------------
11. Immediate #<data>
------------------------------------------------------------


+--------------------------------------------------------------------------+
|         Instruction Assembler Syntax
+--------------------------------------------------------------------------+

           Instructions are separated by asterix lines.
****************************************************************************
Add Binary Coded Decimal w/extend

NAME ABCD -- Add binary coded decimal

SYNOPSIS ABCD Dy,Dx
ABCD -(Ay),-(Ax)

Size = Byte

FUNCTION
       Adds the source operand to the destination operand along with
the extend bit, result is stored in the destination location.
The addition is performed using binary coded decimal arithmetic.
The operands, which are packed BCD numbers, can be addressed in
two different ways:

1. Data register to data register: The operands are contained
   in the data registers specified in the instruction.

2. Memory to memory: The operands are addressed with the
   predecremented addressing mode using the address registers
   specified in the instruction.

This operation is a byte operation only.

Normally the Z condition code bit is set via programming before
the start of an operation. That allows successful tests for
zero results upon completion of multiple-precision operations.

FORMAT
       +---------------------------------------------------------------+
       |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
       |---|---|---|---|-----------|---|---|---|---|---|---|-----------|
       | 1 | 1 | 0 | 0 |    Rx     | 1 | 0 | 0 | 0 | 0 |R/M|    Ry     |
       +---------------------------------------------------------------+

R/M = 0 -> data register
R/M = 1 -> address register
Rx:   destination register
Ry:   source register

RESULT
X - Set the same as the carry bit.
N - Undefined
Z - Cleared if the result is non-zero. Unchanged otherwise.
V - Undefined
C - Set if a decimal carry was generated. Cleared otherwise.
****************************************************************************



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 Tags: instruction set, motorola


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