Tecnical manual, commands and controls (by intel)
Tecnical manual of the Intel 8272 FDD Controller Chip. A part from the general description of the chip, it contains diagrams and timing schemas, commands and function usage.
READ, WRITE, SEEK, RECALIBRATE, FORMAT TRACK are some of the explained commands.
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INTEL 8272 Single/Double Density Floppy Disk Controller
+ IBM Compatible in Both Single and + Data Transfers in DMA or Non-DMA Double Density Recording Formats Mode
+ Programmable Data Record Lengths : + Parallel Seek Operations on Up to 128,256,512, or 1024 Bytes/Sector Four Drives
+ Drive Up to 4 Floppy Disks + Compatible with Most Microprocessors Including 8080A, + Data Scan Capability - Will Scan a 8085A,8086 and 8088 Single Sector or an Entire Cylinder's Worth of Data Fields, Comparing on a + Single-Phase 8 MHz Clock Byte by Byte Basics, Data in the Processor's Memory with Data Read + Single +5 Volt Power Supply from the Diskette + Available in 40-Pin Plastic Dual-in -line Package
The 8272 is an LSI Floppy Disk Controller (FDC) Chip, WHICH contains the circulty and control functions for interfacing a processor to 4 Floppy Disk Drives. It is capable of supporting either IBM 3740 single density format (FM),or IBM System 34 Double Density format (MFM) including double sided recording. The 8272 provides control signals which simlify the design of an external phase locked loop, and write precompensation circultry. The FDC simplifies and hanles most of the burdens associated with implementing a Floppy Disk Drive Interface.
INDEX ----- Pin Configuration 8272 Internal Block Diagram 8272 System Block Diagram Description Features 8272 Registers - Cpu Interface Pin Description Chip Commands Polling Feature Of The 8272 Table 1. 8272 Command Set Table 2. Command Mnemonics Command Descriptions Read Data Table 3. Transfer Capacity Table 4. Id Information When Processor Terminates Command Write Data Write Deleted Data Read Deleted Data Read A Track Read Id Format Track Table 5. Sector Size Relationships Scan Commands Table 6. Scan Status Codes Seek Recalibrate Sense Interrupt Status Table 7. Seek Interrupt Codes Specify Sense Drive Status Invalid Table 8. Status Registers
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PIN CONFIGURATION
+---+ +----+ RESET--+1 +---+ 40 +--Vcc _RD--+2 39 +--_RW/SEEK _WR--+3 38 +--LCT/DIR _CS--+4 37 +--FR/STP A0--+5 36 +--MDL DB0--+6 35 +-RDY DB1--+7 34 +--WP/TS DB2--+8 33 +--FLT/TRK0 DB3--+9 32 +--PS0 DB4--+10 31 +--PS1 DB5--+11 30 +--WR DATA DB6--+12 29 +--DS0 DB7--+13 28 +--DS1 DRQ--+14 27 +--HDSEL _DACK--+15 26 +--MFM TC--+16 25 +--WE IDX--+17 24 +--Vc0 INT--+18 23 +--RD DATA CLR--+19 22 +--DW GND--+20 21 +--WR CLK +------------+
8272 INTERNAL BLOCK DIAGRAM
! ! +----------+ +-------+ ! ! ! ! /__\ ! ! /__\ ! ! /__\ ! ! DB0-7<____>! DATA !<___ >!8!<____>! ! \ / ! BUS ! \ / !2! \ / !REGISTERS ! ! BUFFER! !7! ! ! ! ! !2! ! ! ! ! ! ! ! ! +-------+ !I! ! ! -----+ !N! +----------+ TERMINAL ! !T! COUNT \! / !E! +----------+ \/ !R! ! SERIAL !<------- WR CLOCK +--------+ !N! ! INTERFACE!-------> WR DATA DRQ<---! ! !A! /__\ !CONTROLLER!-------> WR ENABLE DACK--->. READ ! !L!<____>! !-------> PRE-SHIFT0 INT<---! WRITE ! ! ! \ / ! !-------> PRE-SHIFT1 ID--->. DMA ! /__\ !B! ! !<------- READ DATA WR--->. CONTROL!<____>!U! ! !<------- DATA WINDOW A0--->! LOGIC ! \ / !S! +----------+-------> Vco SYNC RESET--->! ! ! ! +----------+ ! ! ! ! ! ! +-----+ +---.----+ ! ! ! ! /__! ! /!\ ! ! ! DRIVE !<___!INPUT! ! ! ! /__\ !INTERFACE ! \ ! PORT! ! ! !<____>!CONTROLLER! ! ! ! ! ! \ / ! ! +-----+ CS -----+ ! ! ! ! /\ +-----+ ! ! ! !<-->! !-->DRIVE SEL0 ! ! +----------+ \/ ! OUT !-->DRIVE SEL1 ! ! ! !-->MFM MODE CLK ---> ! ! ! PORT!-->R/W SEEK Vcc ---> ! !-->HEAD LOAD GND ---> ! !-->HEAD SELECT ! !-->LOW ! ! CURRENT/DIRECTION +-----+-->FAULT RESET/STEP
8272 SYSTEM BLOCK DIAGRAM
+------+ ! ! ! CPU ! ! ! +------+ ^ / \ / \ | | | | \ / \ / -------------------------------------------------------- SYSTEM BUS -------------------------------------------------------- ^ ^ / \ / \ / \ / \ | | | | | | | | \ / \ / \ / \ / +----------+ +----------+ DATA +---+ +----------+ ! ! DRQ ! ! WINDOW ! ! ! --+ ! !<--------! !<-----------!FLL!---! ! ! ! ! ! ! ! | ! ! 8237 ! ! 8272 ! +---+ | ! DRIVE ! ! DMA ! _DACK ! ! RD DATA | ! ! !CONTROLLER!-------->! FDC !<------------------ !INTERFACE ! ! ! ! WR DATA ! ! ! ! ! !------------------->! ! ! ! ! ! / ! ! ! !-------->! ! / -----------------! ! +----------+ TC ! !< INPUT CONTROL ! ! ! ! \ -----------------! ! (TERMINAL COUNT)! ! \ ! ! ! ! \ ! ! ! !------------------\ ! ! ! ! OUTPUT CONTROL >! ! +----------+------------------/ +----------+ /
DESCRIPTION
Hand-shaking signals are provided in the 8272 which make DMA operation easy to incorporate with the aid of an external DMA Controller chip, such as the 8237. The FDC will operate in einther DMA or Non-DMA mode. In the Non-DMA mode,the FDC generates interrupts to the processor for every transfer of data byte between the CPU and 8272. In the DMA mode, the processor need only load command into the FDC and all data transfers occur under control of the 8272 and DMA controller.
There are 15 separate commands which the 8272 will execute. Each of these commands require multiple 8-bit bytes to fully specify the operation which the processor wishes the FDC to perform. The following commands are available:
Read Data Write Data Read ID Format a Track Read Deleted Data Write Deleted Data Read a Track Seek Scan Equal Recalibrate (Restore to Track 0) Scan High or Equal Sense Interrupt Status Scan Low or Equal Specify Sense Drive Status
FEATURES
Addres mark detection circultry is internal to the FDC which simlifies the phase locked loop and read electronics. The track stopping rate, head load time, and head unload time may be programmed by user. The 8272 offers many additional features such as multiple sector transfers in both read and write modes with a single command, and full IBM compatibillity in both single (FM) and double density (MFM) modes.
8272 REGISTERS - CPU INTERFACE
The 8272 contain two registers which may accessed by the main system processor: a Status Register and a Data Register. The 8-bit Main Status Register contains the status information of the FDC ,and may be accessed at any time. The 8-bit Data Register ( actually consists of several registers in a stack with only one register presented to the data bus at time), stores data ,commands,parameters, and FDD status information. Data bytes are read out of, or written into, the Data Register in order to program or obtain the results after execution of command. The Status Register may only be read and is used to facilitate the transfer of data between the processor and 8272.
The relationship between the Status/Data registers and the signals _RD,_WR, and A0 is shown below.
+---+-----+-----+---------------------------+ !A0 ! _RD ! _WR ! FUNCTION ! +---+-----+-----+---------------------------+ ! 0 ! 0 ! 1 ! Read Main Status ! ! ! ! ! Register ! +---+-----+-----+---------------------------+ ! 0 ! 1 ! 0 ! illegal ! +---+-----+-----+---------------------------+ ! 0 ! 0 ! 0 ! illegal ! +---+-----+-----+---------------------------+ ! 1 ! 0 ! 0 ! illegal ! +---+-----+-----+---------------------------+ ! 1 ! 0 ! 1 ! Read from Data Register ! +---+-----+-----+---------------------------+ ! 1 ! 1 ! 0 ! Write into Data Register ! ! ! ! ! ! +---+-----+-----+---------------------------+
READY
-------+ NOT+------+ +---------+ +-----+ +-------¸ REQUEST ! ! ! ! ! ! ! ! ! FOR ! RDY! ! ! ! ! ! ! MASTER +----+ +--+ +----+ +------+ ! (RQM) ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! -----+ +----+----+ +-------------------------------------- _WR ! ! ! ! ! ! ! ! ! +-+ +-+ ! ! ! ! ! ! ! ! ! -------+----+------+----------+ +--------+ +-------------- ! ! ! ! ! ! ! ! ! ! ! _RD +-+ +-+ ! ! ! ! ! ! ! ! ! ! +----+----+------+--+----+----+----+-----+----+-+-------+ ! A ! B ! A !B ! A ! C ! D ! C ! D !B! A ! +----+----+------+--+----+----+----+-----+----+-+-------+
NOTE : (A) - DATA REGISTER READY TO BE WRITTEN INTO BY PROCESSOR (B) - DATA REGISTER NOT READY TO BE WRITTEN INTO AT PROCESSOR (C) - DATA REGISTER READY FOR NEXR DATA BYTE TO BE READ BY THE PROCESSOR. (D) - DATA REGISTER NOT READY FOR NEXT DATA BYTE TO BE READ BY PROCESSOR
Pic. STATUS REGISTER TIMING
CHIP COMMANDS
The 8272 is capable of executing 15 different commands. Each command is initiated by a multi-byte transfer from the proaessor, and the result after execution of the command may also be a multi-byte transfer back to the processor. Because of this multi-byte interchange of information between the 8272 and the processor, it is convenient to consider each command as consisting of three phases:
Command Phase: The FDC receives all information required to perform a particular operation from the processor.
Execution Phase: The FDC performs the operation it was instructed to do. Result Phase: After completion of the operation, status and other housekeeping information are made available to the processor.
During Command or Result Phases the Main Status Register (described earlier) must be read by the processor before each byte of information is written into or read from the Data Register. Bits D6 and D7 in the Main Status Register must be in a 0 and 1 state, respectively,before each byte of the command word may be written into the 8272. Many of the commands require multiple bytes, and as a result the Main Status Register must be read prior to each byte transfer to the 8272. On the other hand, during the Result Phase, D6 and D7 in the Main Status Register must both 1's (D6=1 and D7=1) before reading each byte from the Data Register. Note, this reading of the Main Status Register before each byte transfer to the 8272 is required in only the Command and Result Phases, and NOT during the Execution Phase.
During the Execution Phase, the Main Status Register need not be read. If the 8272 is in the NON-DMA Mode, then the receipt of each data byte (if 8272 is reading data from FDD) is indicated by an interrupt signal on pin 18 (INT=1). The generation of Read signal (_RD=0) will reset the interrupt as well as output the Data onto the Data Bus. For example, if the processor connot handle interrupts fast enough (every 13 ms for MFM mode) then it may poll the Main Status Register and then bit D7 (RQM) functions just like the interrupt signal. If a Write Command is in process then the _WR signal performs the reset to the interrupt signal. If the 8272 is in the DMA Mode, no interrupts are generated during the Execution Phase. The 8272 generated DRQ's (DMA Requests) when each byte of data is available. The DMA Controller responds to this request with both a _DACK =0 (DMA Acknowledge) and a _RD = 0 (Read signal). When the DMA Acknowlege signal goes low (_DACK=0) then the DMA Request is reset (DRQ=0). If a Write Command has been prorammed then a _WR signal will appear instead of _RD. After the Execution Phase has been completed (Terminal Count has occurred) then an interrupt will occur (INT=1). This signifies the beginning of the Result Phase. When the first byte of data is read during the Result Phase, the interrupt is automatically reset (INT=0).
It is important to note that during the Result Phase all bytes shown in the Command Table must be read. The Read Data Command, for example, has seven bytes of data in the Result Phase. All seven bytes must be read in order to succesfully complete the Read Data Command. The 8272 will not accept a new command until all seven bytes have been read. Other commands may require fewer bytes to be read during the Result Phase.
The 8272 contains five Status Register. The Main Status Register mentioned above may be read by the processor at any time. The other four Status Registers (ST0,ST1,ST2, and ST3) are only available during the Result Phase, and may be read only after successfully completing command. The particular command which has been executed determines how many of the Status Register will be read.
The bytes of data which are sent to the 8272 in the Result Phase, must occur in the order shown in the Command Table. That is ,the Command Code must be sent first and the other bytes sent in the prescribed sequence. No foreshortening of the Command of Result Phases are allowed. After the last byte of data in the Command Phase is sent to the 8272 the Execution Phase automatically starts. In a similar fashion, when the last byte of data is read out in the Result Phase, the command is automtically ended and the 8272 is ready for a new command. Acommand may be aborted by simply sending a Terminal Count to pin 16 (TC=1). This is convenient means of ensuring that the processor may always get the 8272's attention even if the disk system hangs up in an abnormal manner.
POLLING FEATURE OF THE 8272
After the Specify command has been sent to the 8272, the Drive Select Lines DS0 and DS1 will automatically go into a polling mode. In between commands (and between step pulses in the SEEK command) the 8272 polls all four FDD looking for a change in the Ready line from any of the drives. If the Ready line changes state (usually due to a door opening of closing) then the 8272 will generate an interrupt. When Status Register 0 (ST0) is read (after Sense interrupt Status is issued), Not Ready (NR) will be indicated. The polling of the Ready line by the 8272 occurs continuously between instructions, thus notifying the processor which drives are on or off line.
COMMAND DESCRIPTIONS
During the Commnd Phase, the Main Status Register must be polled by the CPU before each byte is written into the Data Register. The DIO (DB6) and RQM (DB7) bits in the Main Status Register must be in the "0" and "1" states respectivety, before each byte of the command may be written into the 8272. The beginning of the execution phase for any of these commands will chuse DIO and RQM to switch to "1" and "0" states respectively.
READ DATA
A set of nine (9) byte words are required to place the FDC into the Read Data Mode. After the Read Data commands has been issued the FDC loads the head (if it is in the unloaded state), waits the specified head setting time (defined in the Specify Command), and begins reading ID Address Mark and ID fields. When the current sector number ("R") stored in the ID Register (IDR) compares with the sector number read off the diskette, then FDC outputs data (from the data field) byte-byte to the main system via the data bus.
After completion of the read operatipn from the current sector, the Sector Number is incremented by one , and the data from the next sector is read and output on the data bus. This continuous read function is called a "Multi- Sector Read Operation". The Read Data Command may be the receipt of a Terminal Count signal. Upon receipt of this signal, the FDC stops outputting data to the processor, but will continue to read data from the current sector, check CRC (Cyclic Redundancy Count) bytes, and then at the end of the sector terminate the Read Data Command.
The amount of data wchich can be hanled with a single command to the FDC depends upon MT (multo-track), MFM (MFM/FM), and N (Number of Bytes/Sector). Table 3 below shows the Transfer Capacity.
TABLE 3. TRANSFER CAPACITY
+-----------+-------+-------------+---------------------------------+---------+ !Multi-Track! MFM/FM! Bytes/Sector! Maximum Transfer Capacity ! Final ! ! MT ! MFM ! N ! (Bytes/Sector)(Number of Sectors! Sector ! ! ! ! ! ! Read ! ! ! ! ! ! from ! ! ! ! ! ! Diskette! +-----------+-------+-------------+---------------------------------+---------+ ! 0 ! 0 ! 00 ! (128)(26)=3.325 !26 at ! ! 0 ! 1 ! 01 ! (256)(26)=6.656 !Side 0 or! ! ! ! ! !Side 1 ! +-----------+-------+-------------+---------------------------------+---------+ ! ! ! ! ! ! ! 1 ! 0 ! 00 ! (128)(52)=6.656 ! 26 ! ! 1 ! 1 ! 01 ! (256)(52)=13.312 ! at Side1! +-----------+-------+-------------+---------------------------------+---------+ ! ! ! ! !Side 1 ! ! 0 ! 0 ! 01 ! (256)(15)=3.840 ! or 0 ! ! 0 ! 1 ! 02 ! (512)(15)=7.680 ! 15 ! +-----------+-------+-------------+---------------------------------+---------+ ! ! ! ! ! 15 ! ! 1 ! 0 ! 01 ! (256)(30)=7.680 ! at ! ! 1 ! 1 ! 02 ! (512)(30)=15.360 !Side 1 ! +-----------+-------+-------------+---------------------------------+---------+ ! ! ! ! !8 at Side! ! 0 ! 0 ! 02 ! (512)(8)=4.095 !0 or 8 at! ! 0 ! 1 ! 03 ! (1024)(8)=8.192 !Side 1 ! +-----------+-------+-------------+---------------------------------+---------+ ! ! ! ! ! ! ! 1 ! 0 ! 02 ! (512)(16)=8.192 !8 at ! ! 1 ! 1 ! 03 ! (1024)(16)=16.384 !Side 1 ! ! ! ! ! ! ! +-----------+-------+-------------+---------------------------------+---------+
The "multi-track" function (MT) allows the FDC to read data from sides of the diskette. For a particular cylinder, data will be transferred starting at Sector 1,Side 0 and completing at Sector L, Side 1 ( Sector L- last sector on the side). Note, this function pertains to only one cylinder (the same track ) on each side of the diskette.
When N=0, then DTL defines the length which the FDC must treat as a sector. If DTL is smaller than the actual data length in a Sector, the data beyong DTL in the Sector, is not sent to the Data Bus. The FDC reads (internally) the complete Sector performing the CRC check, and depending upon the manner of command termination, may perform a Multi-Sector Read Operation. When N is no-zero, then DTL has no meaning and should be set to 0FFH.
At the completion of the Read Data Command, the head is not unloaded until after Head Unload Time inteval (specified in the Specify Command) has elapsed. If the processor issues another command before the head unloads then the head setting time may be saved between subsequent reads. This time out is particulary valuable when a diskette is copied from one drive to another.
If the FDC detects the Index Hole twice without finding the riht sector, (indicated in "R"), then the FDC sets the ND (No Data) flag in Status Register 1 to a 1 (high), and terminates the Read Data Command. (Status Register 0 also has bits 7 and 6 set to 0 and 1 respectively).
After reading the ID and Data Fields in each sector, the FDC checks the CRC bytes . If a read error is detected (incorrect CRC in ID field), the FDC sets the DE (Data Error) flag in Status Register 1 to a 1 (high), and if a CRC error occurs in the Data Field the FDC also sets the DD(Data Error in Data Field) flag in Status Register 2 to a 1 (high), and terminates the Read Data Command. (Status Register 0 also has bits 7 and 6 set to 0 and 1 respectively)
If the FDC reads a Deleted Data Address Mark off the diskette, and the SK bit (bit D5) in the first Command Word) is not set (SK=0), then the FDC sets the CM (Control Mark) flag in Status Register 2 to a 1 (high), and terminates the Read Data Command,after reading all the data in the Sector. If SK=1, the FDC skips the sector with the Deleted Data Address Mark and reads the next sector.
During disk data transfers between the FDC and the processor, via data bus, FDC must be serviced by the processor every 27 ms in the FM Mode, and every 13 ms in the MFM Mode, or the FDC sets the OR (Over Run) flag in Status Register 1 to a 1 (high), and terminates the Read Data Command.
If the processor terminates a read (or write) operation in the FDC, then the ID information in the Result Phase is dependent upon the state of the MT bit and EOT byte. Table 4 shows the values for C,H,R, and N, when the processor terminates the Command.
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Tags: 8272, chipset, fdd
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