Optimizations for Intel"s 32-Bit Processors

A 49 page guide on Intel Asm Code Optimization

(by bev zaharie)

The Intel386 Architecture Family represents a series of compatible processors including the Intel386, Intel486, and the Pentium processors. The newer members of the family are capable of executing any binaries created for members of previous generations. For example, any existing 8086/8088, 80286, Intel386 (DX or SX), and Intel486 applications will be able to execute on the Pentium processor without any modification or recompilation. However, there are certain code optimization techniques which will make applications execute faster on a specific member of the family with little or no impact on the performance of other members. Most of these optimizations deal with instruction sequence selection and instruction reordering to complement the processor micro architecture.

The intent of this document is to describe the implementation differences of the processor members and the optimization strategy that gives the best performance for all members of the family

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                  Optimizations for Intel's 32-Bit Processors
                               

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Table of Contents

1.  Introduction 	                                                   1
2.  Overview of Intel386, Intel486, Pentium Processors	                   1
2.1. The Intel386 Processor	                                           1
2.1.1.  Instruction Prefetcher	                                           1
2.1.2.  Instruction Decoder	                                           1
2.1.3.  Excution Core	                                                   1
2.2. The Intel486 processor	                                           1
2.2.1.  Integer Pipeline	                                           2
2.2.2.  On-Chip Cache	                                                   2
2.2.3.  On-Chip Floating-Point Unit	                                   2
2.3. The Pentium processor	                                           2
2.3.1.  Integer Pipelines	                                           3
2.3.2.  Caches	                                                           3
2.3.3.  Instruction Prefetcher	                                           3
2.3.4.  Branch Target Buffer	                                           3
2.3.5.  Pipelined Floating-Point Unit	                                   3
3.  Integer Examples	                                                   4
3.1. Code Sequence 1, Intel486 Processor	                           5
3.2. Code Sequence 1, Pentium Processor	                                   6
3.3. Code Sequence 2, Intel486 Processor	                           6
3.4. Code Sequence 2, Pentium Processor	                                   7
3.5. Code Sequence 3, Intel486 Processor	                           7
3.6. Code Sequence 3, Pentium Processor                                    7
4.  Code Generation Strategy	                                           9
5.  Blended Code Generation Consideration	                          10
5.1.  Choice of Index Versus Base Register                                10
5.2.  Addressing Modes and Register Usage	                          10
5.3.  Prefetch Bandwidth	                                          11
5.4.  Alignment	                                                          12
5.4.1.  Code	                                                          12
5.4.2.  Data								  12
5.4.3.  2-Byte Data	                                                  12
5.4.4.  4-Byte Data	                                                  12
5.4.5.  8-Byte Data	                                                  12
5.5.  Prefixed Opcodes	                                                  12
5.6.  Integer Instruction Scheduling	                                  13
5.6.1.  Pairing	                                                          13
5.6.2.  Instruction Set Pairability	                                  13
	5.6.2.1.  Unpairable Instructions (NP)	                          13
	5.6.2.2.  Pairable Instructions Issued to U or V  pipes (UV)      14
	5.6.2.3.  Pairable Instructions Issued ot U pipe (PU)	          14
	5.6.2.4.  Pairable Instructions Issued to V  pipe (PV)	          14
5.6.3.  Unpairability Due to Registers	                                  14
5.6.4.  Special Pairs	                                                  15
5.6.5.  Restrictions on Pair Execution	                                  16
5.7.  Integer Instruction Selection	                                  16
6.  Processor Specific Optimizations	                                  20
6.1.  Pentium Processor Floating Point	                                  20
6.1.1.  Floating-Point Example	                                          20
6.1.2.  FXCH Rules and Regulations	                                  22
6.1.3.  Memory Operands	                                                  23
6.1.4.  Floating-Point Stalls	                                          23
7.  Summary	                                                          26

Appendix A - Instruction Pairing Summary                                 A-1

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